/**
  ******************************************************************************
  * @file    L3GD20.h
  ******************************************************************************
  */ 

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4_DISCOVERY_L3GD20_H
#define __STM32F4_DISCOVERY_L3GD20_H

#ifdef __cplusplus
 extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"

#define L3GD20_CS_LOW()       	GPIO_ResetBits(L3GD20_SPI_CS_GPIO_PORT, L3GD20_SPI_CS_PIN)
#define L3GD20_CS_HIGH()      	GPIO_SetBits(L3GD20_SPI_CS_GPIO_PORT, L3GD20_SPI_CS_PIN)

/**
  * @brief  L3GD20 SPI Interface pins
  */
#define L3GD20_SPI                       SPI1
#define L3GD20_SPI_CLK                   RCC_APB2Periph_SPI1

#define L3GD20_SPI_SCK_PIN               GPIO_Pin_3                 /* PA.05 */
#define L3GD20_SPI_SCK_GPIO_PORT         GPIOB                       /* GPIOA */
#define L3GD20_SPI_SCK_GPIO_CLK          RCC_AHB1Periph_GPIOB
#define L3GD20_SPI_SCK_SOURCE            GPIO_PinSource3
#define L3GD20_SPI_SCK_AF                GPIO_AF_SPI1

#define L3GD20_SPI_MISO_PIN              GPIO_Pin_4                  /* PA.6 */
#define L3GD20_SPI_MISO_GPIO_PORT        GPIOB                       /* GPIOA */
#define L3GD20_SPI_MISO_GPIO_CLK         RCC_AHB1Periph_GPIOB
#define L3GD20_SPI_MISO_SOURCE           GPIO_PinSource4
#define L3GD20_SPI_MISO_AF               GPIO_AF_SPI1

#define L3GD20_SPI_MOSI_PIN              GPIO_Pin_5                  /* PA.7 */
#define L3GD20_SPI_MOSI_GPIO_PORT        GPIOB                       /* GPIOA */
#define L3GD20_SPI_MOSI_GPIO_CLK         RCC_AHB1Periph_GPIOB
#define L3GD20_SPI_MOSI_SOURCE           GPIO_PinSource5
#define L3GD20_SPI_MOSI_AF               GPIO_AF_SPI1

#define L3GD20_SPI_CS_PIN                GPIO_Pin_15                  /* PE.03 */
#define L3GD20_SPI_CS_GPIO_PORT          GPIOA                       /* GPIOE */
#define L3GD20_SPI_CS_GPIO_CLK           RCC_AHB1Periph_GPIOA


/******************************************************************************/
/*************************** START REGISTER MAPPING  **************************/
/******************************************************************************/

/*******************************************************************************
*  WHO_AM_I Register: Device Identification Register
*  Read only register
*  Default value: 0x3B
*******************************************************************************/
#define L3GD20_WHO_AM_I_ADDR               0x0F
#define L3GD20_CTRL_REG1_ADDR              0x20
#define L3GD20_CTRL_REG2_ADDR              0x21
#define L3GD20_CTRL_REG3_ADDR              0x22

#define L3GD20_OUT_X_ADDR                  0x28
#define L3GD20_OUT_Y_ADDR                  0x2A
#define L3GD20_OUT_Z_ADDR                  0x2C


void L3GD20_Init(uint8_t ctrl1);
void L3GD20_ReadGyro(int32_t* out);
void L3GD20_Write(uint8_t* pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite);
void L3GD20_Read(uint8_t* pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead);

#ifdef __cplusplus
}
#endif

#endif /* __STM32F4_DISCOVERY_L3GD20_H */

/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
